[Post #11/38] MOSFET Physical Structure and I-V Characteristics (Large/Small-Signal Models)

CONTENT_START [HERO: A 3D cross-sectional view of an NMOS transistor showing the Gate-Oxide-Substrate sandwich and the inversion layer.]

📘 Microelectronic Circuits Series — Post #11/38 — 6.1-6.3 (Theory)

The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is the fundamental building block of modern computing, serving as the digital switch in your CPU and the analog engine in your signal-processing circuits. Understanding the transition from physical device geometry to the I-V equations is the single most important bridge between physics and circuit-level design.

1. Overview & Background — Why this matters

Think of an NMOS transistor like a bridge over a river. The "river" is the current flowing from the Drain (D) to the Source (S). The "bridge" is the conductive channel formed under the Gate (G). Without any voltage on the gate, the river is frozen, and no one can cross. By applying a positive gate voltage (V_GS), you begin to thaw the ice, eventually forming a bridge that allows current to flow freely. The height of the bridge is set by the threshold voltage, V_th.

Figure 1. NMOS cross-section (source, drain, gate, oxide, substrate)

In analog circuits, we don't just use this as a simple on/off switch; we operate it in the "saturation" region, where the bridge is partially open, allowing us to modulate the current flow precisely with the input signal. This is how we build amplifiers for sensors, communication systems, and high-precision reference circuits.

Historically, the MOSFET was often treated as an ideal device, but as we shrunk features to the nanometer scale, "secondary effects"—like short channels and high electric fields—began to dictate behavior. Mastering these is what separates a student who can solve equations from an engineer who can design a product that actually works in silicon.

[DIAGRAM_1: Cross-section of an NMOS showing the n+ regions, the polysilicon gate, and the oxide layer, plus an IV-curve family highlighting the triode and saturation regions.]

2. How it Works (Physical & Circuit Principles)

The NMOS structure consists of two heavily doped n-type regions (Source and Drain) embedded in a p-type substrate. Between them sits the Gate, separated from the channel region by a very thin layer of silicon dioxide (SiO₂), which acts as an insulator. Because of this oxide, no DC current flows into the gate, which gives the MOSFET its defining advantage: nearly infinite input impedance at DC.

When you apply V_GS > V_th, you create an electric field that repels holes and attracts electrons to the surface of the p-substrate under the oxide. When enough electrons accumulate, they form an n-type "inversion layer" (the channel). Now, the source and drain are connected by this conductive path. The current flowing through this channel is controlled by the voltage difference between the gate and source.

As you increase V_DS while V_GS is held constant, the device operates in the triode (linear) region where it behaves like a voltage-controlled resistor. Once V_DS reaches the "overdrive" voltage (V_GS - V_th), the channel near the drain is "pinched off," and the current saturates. From this point on, the current becomes largely independent of V_DS, allowing us to use the transistor as a current source.

3. Key Design Equations

where μ_n is electron mobility, C_ox is oxide capacitance per unit area, W/L is the device aspect ratio, and this equation defines the Triode Region.

Figure 2. I_D vs V_DS curves parameterized by V_GS (triode, saturation, breakdown)

where λ is the channel-length modulation parameter, accounting for the slight increase in current as V_DS increases in saturation.

where g_m (transconductance) represents the gain sensitivity, describing how effectively the gate voltage controls the output current.

where r_o is the output resistance of the transistor, and V_A is the Early voltage (or inverse of λ) representing how flat the saturation curve is.

4. Worked Numerical Example

Consider an NMOS transistor in a standard 0.18 μm CMOS process with μ_nC_ox = 200 μA/V², V_th = 0.5 V, and a width-to-length ratio W/L = 10 μm / 0.5 μm = 20. We apply V_GS = 1.0 V and V_DS = 1.0 V.

First, check the region of operation: V_GS - V_th = 1.0 - 0.5 = 0.5 V. Since V_DS (1.0 V) is greater than V_GS - V_th (0.5 V), the device is in saturation.

Calculate I_D: I_D = 0.5 × 200 μA/V² × 20 × (0.5 V)² = 100 × 0.25 mA = 25 μA.

If the device has a λ = 0.1 V^-1, the actual current including channel-length modulation is: I_D = 25 μA × (1 + 0.1 × 1.0) = 27.5 μA. The 2.5 μA increase is the result of the channel "shortening" as the depletion region at the drain grows.

[DIAGRAM_2: Small-signal model showing the dependent current source g_m·v_gs in parallel with output resistor r_o.]

5. Design Considerations & Trade-offs

• Overdrive Voltage: Higher V_GS - V_th increases g_m (good for speed/gain) but consumes more power and reduces the available output swing.
• Channel Length (L): Increasing L increases the output resistance r_o (better gain), but it makes the transistor slower due to increased parasitic gate capacitance.
• Width (W): Increasing W boosts g_m and I_D, but it also increases the load on the previous stage, potentially slowing down the entire system.
• Velocity Saturation: In short-channel devices, carriers reach a speed limit; they no longer obey the square-law (V_GS²) but become linear with V_GS, significantly reducing the achievable gain.

6. Where it Shows Up in Practice

This model is the basis for the input stage of the TI OPA340 op-amp, where g_m determines the open-loop gain. It is also used in high-speed SERDES (Serializer/Deserializer) circuits in Apple’s M-series SoCs, where minimizing r_o and managing velocity saturation is critical for 10+ Gbps data rates. Furthermore, threshold voltage trimming in Samsung 5-nm FinFETs relies on this exact physical characterization to ensure consistent I_D across millions of transistors on a single die.

7. Common Pitfalls & Debugging Tips

• ⚠️ Forgetting the Region: Always calculate V_DS,sat = V_GS - V_th before selecting an equation. Assuming saturation when the device is in triode is the most common cause of error in lab simulations.
• ⚠️ Ignoring λ: For precision analog circuits, λ is never zero. Neglecting it leads to massive errors in calculating the gain (A_v = -g_mr_o).
• ⚠️ Subthreshold Leakage: Below V_th, the current isn't zero; it’s exponential. If your low-power design fails, check if the "off" transistors are leaking due to an overly low V_th.

8. Exam & Interview Hot Spots

• 💡 "Draw the small-signal model and explain why r_o is in parallel with the current source." (It models the finite output impedance due to channel modulation).
• 💡 "How does g_m change if you double the current while keeping W/L constant?" (It increases by √2).
• 💡 "Define 'pinch-off' in your own words." (The point where the channel vanishes at the drain end, causing the current to become independent of V_DS).

9. Key Takeaways

• The MOSFET is a voltage-controlled current source in saturation and a voltage-controlled resistor in triode.
• V_th acts as the gatekeeper; until V_GS exceeds it, the channel remains non-conductive.
• The square-law model is a simplification; always watch for velocity saturation in modern, short-channel (sub-0.18 μm) devices.
• Transconductance g_m is your primary tool for signal amplification, while output resistance r_o determines the signal's attenuation.
• Small-signal models allow us to linearize non-linear device behavior to design amplifiers efficiently.

Educational content only. Always verify with datasheets and SPICE simulation before production design.