[Post #13/38] CMOS Common-Source (CS) Amplifier Design Fundamentals

CONTENT_START [HERO_HERE: Schematic showing the core Common-Source NMOS amplifier with a general load impedance Z_L, highlighting the Input and Output nodes.]

📘 Microelectronic Circuits Series — Post #13/38 — 7.1-7.2 (Theory)

The Common-Source (CS) amplifier is the fundamental building block of virtually all analog integrated circuits, serving as the primary voltage gain stage in everything from cellular baseband processors to precision sensor interfaces. Mastering the CS stage is the "make-or-break" threshold for understanding how we transform small, weak electrical signals into meaningful, high-swing outputs in CMOS technology.

1. Overview & Background — Why this matters

Think of the Common-Source amplifier as a sophisticated electronic "valve." Imagine you are operating a high-pressure fire hose (the power supply V_DD). You cannot control the water by grabbing the hose itself; instead, you operate a small, lightweight handle (the gate) that dictates how much water flows from the high-pressure source to the outlet (the drain). Because the handle requires almost no physical effort to move, a tiny movement of your hand results in a massive change in the water flow, providing significant "gain."

Figure 1. CMOS CS amplifier with current-source load and diode-connected load

In the world of microelectronics, the CS stage translates a variation in gate voltage (V_GS) into a large variation in output voltage. This is not just a theoretical construct; this exact topology forms the core of the operational transconductance amplifiers (OTAs) used in your smartphone's audio codec and the gain stages inside high-speed data converters.

[DIAGRAM_1_HERE: Standard NMOS CS amplifier schematic with load resistance R_D]

2. How it Works (Physical & Circuit Principles)

The CS amplifier functions by converting a voltage signal into a current signal (transconductance) and then back into a voltage signal via an output load. The NMOS transistor acts as a voltage-controlled current source. When V_GS increases, the inversion layer in the MOSFET channel grows, increasing the drain current I_D. This current flows through the load resistor R_D, causing the voltage at the drain to drop because V_out = V_DD - I_DR_D.

The small-signal gain is defined as the change in output voltage divided by the change in input voltage. Because an increase in V_in causes an increase in I_D, which in turn causes a decrease in V_out, the CS stage is inherently an inverting amplifier, indicated by the negative sign in our gain equations.

where g_m is the transconductance (the sensitivity of current to gate voltage) and r_o is the small-signal output resistance of the MOSFET due to channel-length modulation.

💡 Intuition: g_m is the "slope" of the I_D vs V_GS curve; it tells you how much current "kick" you get for every millivolt of gate control. If you have a steeper slope, you get more gain for the same amount of input signal.

3. Key Design Equations

For a resistive load R_D (ignoring r_o for simplicity):

Figure 2. Output voltage swing showing V_DS(sat) headroom

where g_m = 2I_D / (V_GS - V_TH), representing the conversion efficiency of the MOSFET.

For an ideal current source load (active load):

where r_o = 1 / (λI_D), defining the maximum intrinsic gain achievable by the transistor alone.

For a diode-connected load (PMOS):

where the gain depends solely on the ratio of device dimensions and mobilities rather than absolute current values.

4. Worked Numerical Example

Consider a 180-nm CMOS process where V_DD = 1.8 V, I_D = 100 μA, and the device has a transconductance g_m of 1 mA/V. We wish to design a gain of -10.

Step 1: Calculate the required load R_D using the resistive gain formula: R_D = |A_v| / g_m = 10 / (1 × 10^-3 S) = 10 kΩ.

Step 2: Check headroom. The DC output voltage V_out = V_DD - I_DR_D = 1.8 V - (100 μA × 10 kΩ) = 1.8 V - 1.0 V = 0.8 V. Since 0.8 V is greater than the overdrive voltage (~0.2 V), the transistor remains in saturation, which is valid.

[DIAGRAM_2_HERE: Output swing graph showing V_out saturation limits and the linear swing region]

5. Design Considerations & Trade-offs

• Gain vs. Headroom: Increasing R_D increases gain but drags the output DC level closer to ground, limiting the maximum output voltage swing before the transistor enters the triode region.
• Resistive vs. Active Loading: Resistive loads are stable but occupy huge silicon area; active loads (current sources) provide high gain in a small footprint but reduce the available output signal swing (headroom).
• The Diode-Connected Load: Excellent for high-speed applications where you need low impedance, but it inherently limits the maximum voltage gain to a value typically < 5.
• Output Resistance: In deep sub-micron processes, r_o is small; you must account for it, or your predicted gain will be significantly higher than your measured gain.

6. Where it Shows Up in Practice

The CS amplifier is the "workhorse." You will find it as the primary gain stage in the **Texas Instruments OPA350** series, where it is used to drive output current. It is also the fundamental cell used in the design of the **LDO (Low-Dropout) regulators** found in almost every power management unit (PMU) within modern SoCs like the **Apple M-series chips**.

7. Common Pitfalls & Debugging Tips

• ⚠️ Forgetting r_o: In advanced nodes (e.g., 28 nm), r_o is low. If you ignore it, you will overestimate your gain by 30-50%. Always check if your load impedance is significantly smaller than the transistor's intrinsic r_o.
• ⚠️ Bias Sensitivity: The gain g_m is dependent on I_D. If your bias current moves due to temperature changes, your gain will drift significantly. Consider using constant-g_m biasing circuits.

8. Exam & Interview Hot Spots

• 💡 "If you double the width (W) of the transistor while keeping I_D constant, what happens to g_m and A_v?" (g_m increases by √2, so gain increases by √2).
• 💡 "Why is the gain of a diode-connected load limited?" (Because g_m is physically constrained by the device geometry and current, preventing the "infinite" impedance of an ideal current source).
• 💡 "How does the output voltage swing change as you increase R_D?" (The swing shrinks because the quiescent point drops, hitting the triode edge sooner).

9. Key Takeaways

• The CS stage provides voltage gain by converting gate-voltage fluctuations into drain-current fluctuations.
• Gain is directly proportional to g_m and the total load impedance at the drain.
• Resistive loads are easy to use but sacrifice headroom; active loads provide higher gain but require more complex biasing.
• Always verify that the output DC bias point maintains the transistor in the saturation region (V_DS ≥ V_GS - V_TH).
• The inversion from input to output is a fundamental characteristic of the common-source configuration.

Educational content only. Always verify with datasheets and SPICE simulation before production design.