[Post #18/38] Cascode Stage and Current Mirror — Building Blocks of Analog IC

CONTENT_START [HERO_HERE: A clean, high-contrast schematic showing a folded-cascode input stage transitioning into a Wilson current mirror.]

📘 Microelectronic Circuits Series — Post #18/38 — 9.1-9.3 (Key)

The cascode and the current mirror are the "DNA" of analog IC design; without them, we would have no high-gain amplifiers or precision voltage references. These building blocks transform primitive, non-ideal transistors into sophisticated sub-circuits capable of high output impedance and reliable bias distribution in monolithic chips.

1. Overview & Background — Why this matters

Think of a simple Common-Source (CS) amplifier as a person trying to push a heavy cart uphill while someone else is constantly pushing back. The "pushing back" is the finite output resistance of the transistor—it limits how much gain you can achieve. A cascode stage is like putting a second person in a rigid chain behind the first, bracing them so they can focus entirely on driving the load without being perturbed by the erratic bumps in the road.

Figure 1. Cascode amplifier circuit (M1 as CS, M2 as CG)

Historically, as semiconductor processes scaled down, individual transistors became "leaky" and less like ideal current sources. Designers needed a way to reclaim the lost gain. By stacking transistors, we create a structure where one stage shields the other from voltage swings, effectively multiplying the resistance seen at the output. This technique is ubiquitous in everything from the input stages of precision operational amplifiers (like the TI OPA277) to high-speed RF front-ends.

Current mirrors, conversely, are the "tax collectors" of the chip. In an IC, you don't use resistors to set bias currents everywhere because resistors consume too much area and are notoriously inaccurate. Instead, you create one precise "reference" current and copy it across the chip. It’s like a master clock signal for power; you provide the current once, and the mirror distributes it to every sub-block needing a bias.

[DIAGRAM_1_HERE: Schematic showing an NMOS cascode (M1 as CS, M2 as CG) with labels for r_o1 and r_o2.]

2. How it Works (Physical & Circuit Principles)

The Cascode stage is conceptually a Common-Source (CS) amplifier driving a Common-Gate (CG) amplifier. The CS transistor (M1) converts input voltage to current. The CG transistor (M2) acts as a current buffer. Because the CG input impedance is extremely low (1/g_m2), the voltage swing at the drain of M1 is nearly eliminated. This completely suppresses the Miller effect—the parasitic capacitance that usually kills bandwidth by appearing magnified at the input.

The Current Mirror relies on the matching of two identical transistors sharing the same V_GS. If V_GS1 = V_GS2, then I_D2 must equal I_D1, provided the transistors are identical. In practice, we scale the widths (W) to get a ratioed current. The "Wilson" mirror improves this by using negative feedback to force the collector/drain voltages to match, neutralizing the channel-length modulation effect that plagues simple mirrors.

where g_m is the transconductance of the CG device, r_o2 is the output resistance of the CG device, and r_o1 is the resistance of the CS device. This multiplication factor allows us to achieve gains in the thousands from a single stage.

💡 Intuition: The cascode "stiffens" the circuit. Because the top transistor holds its drain voltage constant, the bottom transistor is "tricked" into thinking it's in a much more ideal operating environment, resulting in a nearly flat I-V curve.

3. Key Design Equations

For a MOSFET current mirror:

Figure 2. MOS simple current mirror vs cascode current mirror comparison

where I_ref is the reference current and W/L is the aspect ratio of the transistors; this defines the mirror ratio based on geometric scaling.

For a BJT mirror with finite beta (β):

where β is the common-emitter current gain, illustrating the base current error; note that this error decreases as β increases.

For the output resistance of a cascode:

where the last term dominates, showing why the cascode is so powerful for high-impedance nodes.

4. Worked Numerical Example — Calculate it yourself

Let's design a simple NMOS current mirror in a 180-nm process. V_DD = 1.8 V, I_ref = 50 μA, and we want I_out = 100 μA. We choose L₁ = L₂ = 0.5 μm (to reduce channel-length modulation). If W₁ = 10 μm, then:

Step 1: Determine the ratio. We need I_out / I_ref = 2. Therefore, (W/L)₂ must be twice (W/L)₁.

Step 2: Calculate W₂. Since L is identical, W₂ = 2 × W₁ = 20 μm.

Step 3: Check headroom. Ensure V_DS2 > V_GS - V_TH. If V_GS is 0.7 V and V_TH is 0.5 V, V_DS2 must be at least 0.2 V. If our output node falls below 0.2 V, the mirror exits saturation and the current drops significantly.

[DIAGRAM_2_HERE: Plot of I_out vs. V_out for a simple mirror vs. a cascode mirror, showing the much steeper and flatter saturation region.]

5. Design Considerations & Trade-offs

• Voltage Headroom: Cascoding requires more vertical "space." Each stacked transistor consumes V_DS,sat. In low-voltage processes (0.9 V), you might not have enough room to stack two transistors and still keep them in saturation.
• Output Resistance vs. Speed: While higher R_out is great for gain, it creates a very low-frequency dominant pole at the output node, which can slow down your circuit or cause oscillation.
• Matching: Current mirrors rely on layout matching. Always use common-centroid patterns to ensure that gradients in doping or temperature affect both transistors equally.
• Channel Length (L): Use a larger L than the minimum feature size. This increases r_o (improving current accuracy) but sacrifices speed (higher gate capacitance).

6. Where it Shows Up in Practice

The cascode is the secret sauce in the "Folded Cascode" topology found in the input stages of high-speed op-amps like the National Semiconductor (now TI) LM6171. In data converters (ADCs/DACs), current mirrors are used in the "Current Steering" DAC architecture, where arrays of mirrors are switched to create high-precision analog signals. Every modern CMOS process utilizes these structures in internal bandgap voltage references.

7. Common Pitfalls & Debugging Tips

• ⚠️ The "Saturation" Trap: A mirror that isn't outputting the expected current is almost always pulled out of saturation by a load voltage that is too low. Check your DC operating points in the simulator.
• ⚠️ Beta Mismatch (BJT): In BJT mirrors, the base currents of the output transistors steal current from the reference. If you need high precision, use a buffer transistor (the Wilson mirror) to sink that base current.

8. Exam & Interview Hot Spots

• 💡 "How does a cascode improve output resistance?" (Answer: It buffers the drain voltage of the bottom transistor, keeping its I_D constant despite output voltage fluctuations).
• 💡 "What is the minimum voltage the drain of an NMOS mirror can reach?" (Answer: V_DS,sat, or V_GS - V_TH).
• 💡 "Why do we use long L for current mirrors?" (Answer: To minimize channel-length modulation, i.e., to keep the I-V slope flat).

9. Key Takeaways

• The cascode stage suppresses the Miller effect and boosts gain by increasing output resistance by a factor of g_mr_o.
• Current mirrors provide a scalable, area-efficient way to bias circuits without relying on bulky, inaccurate resistors.
• Always prioritize matching in layout—a current mirror is only as accurate as the physical symmetry of its transistors.
• Voltage headroom is the primary trade-off; adding cascodes increases gain but reduces the allowable signal swing.
• Wilson and Widlar mirrors provide solutions to specific BJT and MOS accuracy limitations, respectively.

Educational content only. Always verify with datasheets and SPICE simulation before production design.