[Post #20/38] MOS Differential Pair Analysis and Common-Mode Rejection (CMRR)

CONTENT_START [HERO_HERE: A high-level visual depicting a balanced seesaw (the diff-pair) supported by a weight (the tail current source), where the tilt represents differential signaling.]

📘 Microelectronic Circuits Series — Post #20/38 — 10.3-10.5 (Theory)

The MOS differential pair is the fundamental building block of all modern analog integrated circuits, from precision operational amplifiers to high-speed data converters. Mastering this structure is the gateway to understanding how we process analog signals in an environment plagued by power supply noise and thermal fluctuations.

1. Overview & Background — Why this matters

Think of a differential pair like a perfectly balanced scales of justice. If you add the same amount of weight to both pans (a common-mode signal), the balance remains horizontal; if you add weight to one side and remove it from the other (a differential signal), the balance tips. In microelectronics, this "scales" structure allows us to ignore noise that affects both inputs equally—like power supply ripples—while amplifying the tiny difference between two signals.

Figure 1. MOS differential pair circuit with tail current source R_SS

This topology serves as the input stage for virtually every op-amp, such as the classic TI OPA211 or the input stage of high-speed comparators used in SAR ADCs. By "subtracting" the noise before it enters the amplification chain, the differential pair acts as a natural gatekeeper, ensuring that only the intentional information (the difference) propagates through the system.

[DIAGRAM_1_HERE: A schematic of an NMOS differential pair showing two input transistors M1/M2, drain resistors R_D, and a tail current source I_SS at the common source node.]

2. How it Works (Physical & Circuit Principles)

The MOS differential pair functions through the elegant steering of a fixed total tail current, I_SS. When the input voltages V_G1 and V_G2 are equal, the current I_SS splits precisely in half between the two branches. As soon as one gate voltage rises slightly relative to the other, the corresponding MOSFET works harder, drawing more current away from its partner. This "see-saw" effect converts the gate-to-gate voltage difference into a significant current imbalance at the drains.

The large-signal behavior is governed by the square-law characteristic of the MOSFET in saturation. The currents in the two transistors are linked by the constraint that their sum must always equal I_SS. Because the transconductance g_m is proportional to the square root of the drain current, the sensitivity of the circuit to differential inputs is maximized when the transistors are operating in the saturation region.

where I_D is the drain current, k'_n is the process transconductance parameter, W/L is the transistor aspect ratio, and V_TH is the threshold voltage.

💡 Intuition: The differential pair is essentially a current-steering valve; it doesn't create current, it simply chooses how to divide a fixed supply of it based on which input is "stronger."

3. Key Design Equations

The differential gain, A_dm, represents how effectively the circuit translates a difference in input voltage into an output voltage swing.

Figure 2. CMRR vs tail resistance R_SS graph

where g_m is the transconductance of each input MOSFET, and R_D is the load resistance at the drain.

The common-mode gain, A_cm, describes how much unwanted noise (common to both inputs) appears at the output.

where R_SS is the output resistance of the tail current source; a higher R_SS forces the common-source node to track the input common-mode voltage, suppressing gain.

The Common-Mode Rejection Ratio (CMRR) is the figure of merit for how well the pair ignores noise.

where g_mR_SS represents the product of the input stage's transconductance and the current source's output impedance.

4. Worked Numerical Example — Calculate it yourself

Consider a 180-nm CMOS process where I_SS = 500 μA (split as 250 μA per side). Let W/L = 20/0.5, k'_n = 200 μA/V², and R_D = 10 kΩ. We use a current source with an output resistance R_SS = 200 kΩ.

1. First, find g_m: g_m = √ (2 · k'_n · W/L · I_D) = √ (2 · 200μ · 40 · 250μ) = 2 mA/V.

2. Calculate A_dm: A_dm = -g_m · R_D = -(2 mS) · (10 kΩ) = -20 V/V.

3. Calculate A_cm: A_cm ≈ -R_D / (2 · R_SS) = -10k / 400k = -0.025 V/V.

4. Finally, CMRR = |20 / 0.025| = 800. In decibels, 20 · log₁₀(800) ≈ 58 dB. This means the circuit is 800 times more sensitive to differential signals than to common-mode interference.

[DIAGRAM_2_HERE: A plot of differential output voltage vs. input differential voltage, highlighting the linear range and the clipping at full current steering.]

5. Design Considerations & Trade-offs

• R_SS Maximization: Increasing the output resistance of the tail current source (e.g., using a cascode current source) is the most direct way to boost CMRR without impacting differential gain.
• Load Balancing: Any mismatch between the two R_D resistors directly converts common-mode voltage into differential output, drastically lowering the effective CMRR.
• Transistor Matching: Mismatch in V_TH or W/L between the two input transistors creates an "input offset voltage," which limits the minimum detectable signal.
• Headroom Trade-off: Making R_D larger increases gain but consumes more DC voltage headroom, potentially pushing the MOSFETs out of saturation.

6. Where it Shows Up in Practice

The differential pair is the core of the TI INA240, an industry-standard current-sense amplifier. By using a precisely matched differential pair at the input, this IC can measure micro-volt drops across a shunt resistor even in the presence of 80V common-mode voltage on the power line. Similarly, inside the Apple M-series SoCs, differential input stages are used in the PLL (Phase-Locked Loop) error amplifiers to ensure the internal clock remains jitter-free despite high-frequency digital switching noise elsewhere on the chip.

7. Common Pitfalls & Debugging Tips

• ⚠️ Tail Current Saturation: If your input common-mode range is too wide, the tail current source will lose its voltage headroom and become a simple resistor, causing CMRR to collapse. Check the V_DS of your current source transistor.
• ⚠️ The "Body Effect": In many processes, the source of the input MOSFETs is not tied to the body. This shifts V_TH as the common-mode level changes, which can lead to non-linear gain. Always check if your design requires a bulk-source connection.

8. Exam & Interview Hot Spots

• 💡 "Why does CMRR degrade at high frequencies?" (Because the parasitic capacitance at the common-source node provides a low-impedance path for common-mode noise).
• 💡 "What happens to the differential pair if the tail current source is replaced by a simple resistor?" (The common-mode gain increases significantly, and CMRR drops to ~1, effectively becoming useless).
• 💡 "Does the differential pair work if I_SS is zero?" (No, the transistors will be in cutoff; a minimum tail current is required to maintain the transconductance g_m).

9. Key Takeaways

• The differential pair is an inherently balanced, symmetric circuit that separates signals into common-mode and differential components.
• Differential gain is proportional to the transconductance and the load resistance.
• High CMRR is achieved by maximizing the output impedance of the tail current source.
• Real-world performance is dominated by component mismatches (R_D and MOSFET W/L variations).
• The circuit effectively "subtracts" common-mode noise, making it the primary choice for noisy system-on-chip environments.

Educational content only. Always verify with datasheets and SPICE simulation before production design.