[Post #19/38] Differential Amplifier Basics and the BJT Differential Pair

CONTENT_START [HERO_HERE: A high-quality render of a symmetric BJT differential pair with a current source tail, showing balanced signal paths.]

📘 Microelectronic Circuits Series — Post #19/38 — 10.1-10.2 (Theory)

The differential amplifier is the bedrock of analog design, serving as the input stage for virtually every operational amplifier and high-speed comparator. Mastering this circuit is essential because it allows us to extract signal information while ignoring the environmental "garbage"—like power supply noise or electromagnetic interference—that plagues precision measurements.

1. Overview & Background — Why this matters

Think of differential signaling like a pair of high-wire artists holding a balance pole. If the whole circus tent sways (representing common-mode noise like power supply ripples), the artists sway together; their relative position—the signal they care about—remains unchanged. In electronics, we don't measure the voltage of a single wire relative to an unstable "ground"; we measure the difference between two wires. This is how high-speed data moves across cables (like HDMI or Ethernet) without being corrupted by the massive amounts of electrical noise present in your computer or router.

Figure 1. BJT differential pair (Q1, Q2, tail current source I_EE, R_C)

Historically, the differential pair (also known as the "long-tailed pair") replaced single-ended amplifiers in applications requiring high stability. Whether you are designing the front-end of an ECG monitor to detect microvolt-level heart signals amidst the noise of a wall outlet, or a high-speed data converter, the differential pair is the architecture that makes it possible to amplify tiny signals while rejecting massive interference.

[DIAGRAM_1_HERE: Schematic showing two NPN transistors (Q1, Q2) with emitters tied to a current source I_EE and collectors connected to resistors R_C.]

2. How it Works (Physical & Circuit Principles)

The differential pair functions as a "current steering" circuit. Imagine a fixed amount of water flowing through a main pipe (the tail current I_EE). We place a Y-junction with two gates (the transistors). By changing the relative pressure on these two gates—the differential input voltage v_id = v_B1 - v_B2—we divert more water into the left path or the right path. Because the total current is constrained by the current source, as one collector current rises, the other must fall, keeping the sum constant.

When the inputs are equal (common-mode), the tail current splits perfectly in half. When a signal is applied, the exponential relationship between the base-emitter voltage and the collector current drives the steering. If we increase v_B1 relative to v_B2, the current i_C1 grows exponentially, while i_C2 shrinks. This nonlinear behavior is what allows the differential pair to act as an amplifier, but it also creates a limitation: if the difference v_id exceeds a certain range, one transistor will completely turn off and "hog" the entire current, causing the amplifier to lose its linear gain.

where I_EE is the total tail current, g_m = I_C/V_T is the transconductance of each transistor, and v_id is the differential input voltage.

💡 Intuition: The "differential" part rejects noise because if a noisy signal (common-mode) moves both bases up by the same amount, the tail current source prevents the collector currents from changing, meaning the output (taken as the difference between collectors) sees zero change.

3. Key Design Equations

The differential gain A_dm is the ratio of the output voltage to the input difference voltage under ideal conditions.

Figure 2. Differential input vs output current transfer curve (tanh shape)

where g_m is the small-signal transconductance of one transistor and R_C is the collector load resistance.

The input common-mode range (ICMR) defines the voltage limits within which the circuit stays active.

where V_CS is the minimum voltage required to keep the current source transistor in saturation and V_BE,on is the turn-on voltage of the pair (~0.7 V).

The collector currents during differential signal application are related to the total tail current.

This implies that for small signals, the currents are symmetric around the bias point I_EE/2.

4. Worked Numerical Example — Calculate it yourself

Consider a BJT differential pair in a standard IC process. We have I_EE = 1 mA and R_C = 5 kΩ. Each transistor is biased at I_C = 0.5 mA.

First, calculate the transconductance: g_m = I_C / V_T = 0.5 mA / 26 mV ≈ 19.2 mA/V. Next, find the differential gain: A_dm = -g_m · R_C = -(19.2 mS) · (5 kΩ) = -96 V/V.

If we apply a differential input v_id of 10 mV, the output voltage swing is v_o = A_dm · v_id = -96 · 10 mV = -960 mV. This shows how a small 10 mV input is amplified to nearly 1 V, a standard signal level for subsequent stages.

[DIAGRAM_2_HERE: Plot of collector currents vs. v_id, showing the tanh-like saturation curve and the linear region around zero.]

5. Design Considerations & Trade-offs

• Gain vs. Supply Headroom: Increasing R_C boosts gain but forces the collectors to sit at a lower DC voltage, potentially pushing the transistors into saturation (where they stop acting as amplifiers).
• Tail Current Source Impedance: A finite resistance in the tail source allows common-mode noise to leak into the output; an ideal current source (infinite impedance) is required for perfect common-mode rejection.
• Linearity: For larger inputs, the exponential behavior introduces distortion; keeping v_id ≪ 2V_T (52 mV) is critical for keeping the circuit linear.
• Device Matching: Any mismatch between the two transistors (like variations in I_S or β) results in a DC offset, where the output is non-zero even when v_id = 0.

6. Where it Shows Up in Practice

The input stage of the classic TI LM741 and the modern OPA211 op-amps are based on this topology. It is also the fundamental block in high-speed CML (Current Mode Logic) used in fiber-optic transceiver chips, where fast switching and low noise are mandatory for multi-gigabit data streams.

7. Common Pitfalls & Debugging Tips

• ⚠️ Tail Saturation: If the common-mode input voltage is too low, the tail current source enters the triode region, killing the gain. Always check the V_CE of the tail transistor.
• ⚠️ Asymmetric Layout: On-chip, if one transistor is physically hotter or closer to a noisy line than the other, the CMRR (Common-Mode Rejection Ratio) will plummet. Use interdigitated layout techniques to ensure physical symmetry.

8. Exam & Interview Hot Spots

• 💡 "Why is the gain of a differential pair exactly half that of a common-emitter amplifier with the same R_C?" (Because only half the current flows through each side at balance).
• 💡 "How does the tail resistance R_EE affect CMRR?" (The CMRR is roughly g_mR_EE; higher R_EE effectively isolates the common-mode noise).

9. Key Takeaways

• Differential signaling relies on the difference between two signals, allowing for high noise rejection.
• The current source "tails" the pair, forcing the sum of the currents to be constant.
• Differential gain is proportional to the transconductance of the transistors and the load resistance.
• Nonlinear current steering occurs as the input difference moves the circuit away from the bias point.
• Matching is the primary challenge in integrated circuit design for this stage.

Educational content only. Always verify with datasheets and SPICE simulation before production design.