[Post #24/38] CB/CG and Cascode Stage High-Frequency Response (Practical Part 2)

CONTENT_START [HERO_HERE: A high-frequency Bode plot showing the Pole-Splitting suppression achieved by a Cascode configuration vs. a standard CS stage.]

📘 Microelectronic Circuits Series — Post #24/38 — 11.5-11.7 (Advanced)

This chapter is the "holy grail" for high-speed analog design. When moving from low-frequency DC analysis to the GHz regime, the parasitic C_gd of your transistors acts like a bridge that drags your performance down via the Miller Effect; mastering the Cascode topology is the primary engineering technique used to dismantle that barrier in every modern RF and broadband amplifier.

1. Overview & Background — Why this matters

Think of the Miller Effect as a "feedback tax" on your circuit's bandwidth. Imagine trying to drive a car (the input signal) while a passenger in the back seat (the output signal) is pulling on the steering wheel in the opposite direction. Because the output is inverted relative to the input, the small capacitor C_gd between them effectively grows into a massive burden—a "phantom capacitor" C_M = C_gd(1 + A_v)—that acts as a massive speed bump at the input node. In high-gain stages, this effectively kills the frequency response.

Figure 1. Cascode high-frequency model emphasizing M1 drain node

The Cascode topology—a Common-Source (CS) stage feeding into a Common-Gate (CG) stage—is like adding a bodyguard (the CG transistor) to stand between the driver (the input) and the chaotic feedback. By pinning the drain of the CS device to a fixed low-impedance node, the CG stage prevents the output voltage from swinging at the CS drain. Since the voltage swing at the drain is effectively zero, the "phantom capacitor" never forms, allowing the amplifier to operate at frequencies near the transition frequency (f_T) of the process.

This topology is the bedrock of wideband design, appearing in everything from high-speed optical transceivers to the front-ends of satellite communication receivers where we need massive gain without sacrificing the high-frequency cutoff.

[DIAGRAM_1_HERE: Schematic showing a CS stage with its Miller capacitance C_gd compared to a Cascode stage where the CS drain node is kept at a low impedance by the CG stage.]

2. How it Works (Physical & Circuit Principles)

In a simple Common-Source amplifier, any change in output voltage (ΔV_out) is reflected back to the input node through C_gd. If we have a gain of -10, a 1 V swing at the output forces 11 V of swing across the input capacitor. This is the Miller effect. In a Cascode, the Common-Gate (CG) transistor acts as a current buffer. It presents an input impedance of approximately 1/g_m to the drain of the CS transistor.

Because this 1/g_m impedance is so low, the voltage gain of the first (CS) stage is restricted to roughly g_m1 × (1/g_m2), which is close to unity (or even less). Because the gain is low, the Miller multiplication of C_gd1 is suppressed; the effective input capacitance becomes essentially C_gs1 + 2C_gd1. This removes the dominant pole that usually cripples wideband amplifiers.

Furthermore, the CG stage itself is immune to the Miller effect because its gain node is at the drain, but its input (the source) is isolated by the low-impedance nature of the stage itself. The overall structure pushes the secondary poles to much higher frequencies, drastically widening the bandwidth.

where g_m is the transconductance, r_o is the small-signal output resistance, and R_L is the load resistance; this equation illustrates that the Cascode provides high gain similar to a single stage but with significantly reduced Miller-effect bandwidth degradation.

💡 Intuition: The Cascode is a "Voltage-to-Current-to-Voltage" converter; by converting the signal to current immediately after the first stage, we prevent the output voltage from ever "seeing" the input gate.

3. Key Design Equations

where R_sig is the source resistance, demonstrating that the input pole is extended by minimizing the effective Miller capacitance.

Figure 2. Bode plot comparison of CS, CB, and cascode stages

where r_out is the output impedance of the cascode (approx. g_m2 r_o1 r_o2) and C_L is the total load capacitance, confirming that the output pole is determined primarily by the high output resistance.

where \omega_z is the Right-Half-Plane (RHP) zero, a phase-degrading term that appears at high frequencies due to the feedthrough of the CG transistor.

4. Worked Numerical Example

Consider a 65-nm CMOS process. Let I_D = 1 mA, g_m1 = g_m2 = 10 mS. Assume C_gd1 = 5 fF, C_gs1 = 20 fF, and R_sig = 50 Ω.

First, calculate the effective Miller multiplication in a standard CS stage with gain A_v = 10: C_eff = 20 + 5(1+10) = 75 fF. The input pole is at ω = 1 / (50Ω × 75fF) = 266 Grad/s.

Now, calculate for the Cascode: since the CS drain sees 1/g_m2 = 100 Ω, the local gain is 10 mS × 100 Ω = 1. The effective input capacitance becomes C_eff = 20 + 5(1+1) = 30 fF. The new input pole is at ω = 1 / (50Ω × 30fF) = 666 Grad/s. By moving the pole from 266 to 666 Grad/s, we have more than doubled the bandwidth while maintaining high gain.

5. Design Considerations & Trade-offs

• Headroom: Cascoding requires stacking transistors, meaning you need more V_DD. In low-voltage processes (e.g., 0.9 V), this becomes a major limitation.
• Output Swing: Each transistor requires a V_DS,sat, reducing the total available voltage swing at the output compared to a simple CS stage.
• Bias Stability: The gate of the CG transistor must be tightly controlled by a stable bias voltage; noise on this node couples directly to the output.
• Noise: The CG transistor adds thermal noise, though it is usually dominated by the input CS device in high-gain designs.

6. Where it Shows Up in Practice

The Cascode is ubiquitous in high-frequency integrated circuits. You will find it in the low-noise amplifier (LNA) input stage of the Qualcomm Snapdragon RF front-end, where gain and bandwidth are critical. It is also standard in the operational transconductance amplifiers (OTAs) used in high-speed pipeline ADCs (e.g., Analog Devices AD9268), where high DC gain is required to reduce settling error in high-speed switched-capacitor circuits.

7. Common Pitfalls & Debugging Tips

• ⚠️ Oscillation: If the gate of the CG transistor is not properly bypassed to ground with a large capacitor, it acts as a high-impedance node, causing the circuit to oscillate or gain-peak unpredictably.
• ⚠️ Voltage Saturation: Always calculate the V_DS of the CS device carefully; if the bias point puts it in the linear region, your gain will vanish and your bandwidth will collapse.

8. Exam & Interview Hot Spots

• 💡 "Why does the Cascode configuration improve the Power Supply Rejection Ratio (PSRR)?" (Answer: It acts as an isolation stage, preventing supply fluctuations from coupling through the output resistance.)
• 💡 "Does the Cascode increase the output resistance?" (Yes, it increases it by a factor of roughly g_mr_o, which is essential for high DC gain.)

9. Key Takeaways

• Cascode stages eliminate the Miller Effect by pinning the drain voltage of the input transistor.
• The effective input capacitance is reduced to roughly C_gs + 2C_gd.
• The tradeoff for high-frequency bandwidth is a reduction in available output voltage headroom.
• The RHP zero (arising from C_gd2) limits the ultimate frequency of the stage.
• Cascode = CS + CG is the fundamental unit for wideband amplifier design.

Educational content only. Always verify with datasheets and SPICE simulation before production design.