[Post #23/38] CE & CS Stage Frequency Response (Practical Part 1)

CONTENT_START [HERO_HERE: Conceptual schematic showing the Miller effect as a magnifying lens placed between the gate and drain nodes.]

📘 Microelectronic Circuits Series — Post #23/38 — 11.4 (Advanced)

High-frequency performance is the ultimate constraint in analog design. While DC gain is a matter of biasing, the speed at which a circuit can process signals—its bandwidth—is governed by the parasitic capacitors lurking within the device structure and the PCB traces themselves. This post dissects the frequency response of the common-source (CS) stage, moving from textbook models to the realities of parasitic extraction in tools like KiCad.

1. Overview & Background — Why this matters

Think of the Miller effect like a person trying to walk through a crowded lobby while carrying a long, horizontal pole. If you try to rotate or move the pole, its apparent weight seems much heavier than it actually is because of the leverage at the ends. Similarly, the gate-to-drain capacitance (C_gd) in a MOSFET acts like that pole; because the drain voltage swings in the opposite direction of the gate voltage with high gain, the tiny physical capacitance is effectively "multiplied" by the gain of the stage, creating a massive load on the input signal source.

Figure 1. CS-stage high-frequency small-signal equivalent (C_gs, C_gd, g_m·v_gs)

Every CMOS operational amplifier, video buffer, and RF front-end is subject to these high-frequency limitations. Understanding the pole-splitting nature of the CS stage is the difference between a stable, wide-band design and a circuit that rings, oscillates, or simply fails to amplify high-speed data. This analysis is the foundation for understanding why internal compensation capacitors are added to multi-stage op-amps (like the classic 741) to ensure global stability.

[DIAGRAM_1_HERE: Small-signal model of a CS stage showing C_gs, C_gd, and the dependent current source g_m·V_gs.]

2. How it Works (Physical & Circuit Principles)

In a common-source stage, the transistor is not just a voltage-controlled current source; it is a complex network of internal capacitors. The gate-to-drain capacitance (C_gd) acts as a feedback bridge. When a signal is applied to the gate, the drain responds with an inverted and amplified voltage. This creates a virtual "stretching" of the capacitance, as the current flowing through C_gd is driven by both the input voltage and the amplified output voltage.

The input signal sees this combined effect, resulting in an effective input capacitance C_in,eff ≈ C_gs + C_gd(1 + |A_v|). Because the signal source usually has a finite output resistance (R_S), this massive effective capacitance forms a low-pass filter (the "input pole"), significantly rolling off the gain before the transistor itself would otherwise reach its limits.

💡 Intuition: The Miller effect is a form of negative feedback that trades bandwidth for voltage gain. By suppressing the gain, we can recover bandwidth; this is exactly what happens in high-frequency "cascode" stages where we eliminate the feedback path.

3. Key Design Equations

where ω_p1 is the -3 dB input corner frequency, R_S is the source resistance, and (1 + g_m R_D) is the Miller-multiplication factor.

Figure 2. CE/CS Bode plot showing two -20 dB/dec poles and an RHP zero

where ω_p2 is the output pole created by the drain-node resistance and the feedthrough capacitor.

where z_R is the right-half-plane (RHP) zero, which introduces a phase shift that degrades stability without providing the magnitude roll-off benefits of a pole.

4. Worked Numerical Example — Calculate it yourself

Consider an NMOS transistor in a 180-nm process: g_m = 5 mS, R_D = 2 kΩ, R_S = 1 kΩ, C_gs = 50 fF, and C_gd = 10 fF.

First, calculate the midband gain: |A_v| = g_m R_D = 5 mS × 2 kΩ = 10.

The Miller-multiplied input capacitance is C_in,eff = 50 fF + 10 fF × (1 + 10) = 50 fF + 110 fF = 160 fF.

The input pole is f_p1 = 1 / (2π × 1 kΩ × 160 fF) ≈ 995 MHz.

The output pole is f_p2 = 1 / (2π × 2 kΩ × 10 fF) ≈ 7.96 GHz.

Notice how the Miller effect pushes the input pole down by nearly an order of magnitude compared to the intrinsic limitations of the device, making it the dominant bottleneck for speed.

[DIAGRAM_2_HERE: Frequency response plot showing the dominant pole at f_p1 and the RHP zero at f_z.]

5. Design Considerations & Trade-offs

• Layout Parasitics (KiCad/Altium): Every millimeter of trace at the drain adds parasitic capacitance to ground (C_pad) and cross-coupling to the gate (C_crosstalk). Always use the "Keepout" layers to minimize trace-to-trace spacing at the high-swing drain node to avoid increasing C_gd via PCB geometry.
• Vias and Inductance: In high-speed designs, a via is not a perfect connection; it is a small inductor. Excessive vias in the signal path can lead to peaking in the frequency response or unexpected resonances at multi-GHz frequencies.
• Signal Source Impedance: To widen bandwidth, reduce R_S. If the driving stage is a high-impedance output, the system will always be slow. Use a source-follower (buffer) to drive the CS stage if high input impedance and high bandwidth are both required.
• Process Scaling: In smaller process nodes (e.g., 28 nm), g_m increases, but so does the density of parasitic metal routing. Accurate parasitic extraction (PEX) is non-negotiable for modern analog layout.

6. Where it Shows Up in Practice

The CS-stage frequency response is the primary limit for the bandwidth of transimpedance amplifiers (TIAs) used in fiber-optic receivers. In these systems, even a few femtofarads of additional parasitic capacitance at the input transistor gate can shift the bandwidth significantly, limiting the total data rate (Gbps). It is also the reason why monolithic RF power amplifiers use neutralized architectures to cancel the effect of C_gd.

7. Common Pitfalls & Debugging Tips

• ⚠️ Ignoring PCB Parasitics: Engineers often simulate a perfect transistor, but the final PCB trace at the drain can add 500 fF of ground capacitance, effectively killing the bandwidth. Always extract parasitics from your KiCad layout.
• ⚠️ The "Floating" Gate: If a gate isn't properly DC biased, small amounts of Miller-coupled drain signal can cause the gate to drift, leading to catastrophic shifts in bias point or oscillation. Use a stiff DC bias network.

8. Exam & Interview Hot Spots

• 💡 "How does the RHP zero impact the phase margin of a feedback amplifier?" (Answer: It adds phase lag, which reduces phase margin and causes instability.)
• 💡 "Why is the input capacitance of a CS stage dependent on the load?" (Answer: The Miller effect; gain increases the voltage swing across the feedback capacitor, demanding more current from the driver.)
• 💡 "What is the most effective way to eliminate the Miller effect?" (Answer: Use a cascode stage to isolate the input from the drain voltage swing.)

9. Key Takeaways

• The Miller effect amplifies C_gd by (1 + gain), making it the dominant input-side capacitor.
• Input pole frequency is set by the source resistance and the total input capacitance (C_gs + Miller-multiplied C_gd).
• The right-half-plane zero (g_m/C_gd) is a fundamental limit to how high we can push the gain-bandwidth product.
• PCB layout (trace spacing and via placement) contributes significantly to parasitic capacitance and must be included in high-frequency analysis.
• Cascode transistors effectively shield the input from the Miller effect by keeping the drain voltage of the gain device constant.

Educational content only. Always verify with datasheets and SPICE simulation before production design.