[Post #35/38] Digital CMOS Circuits: Inverter, NAND, and NOR Analysis

CONTENT_START [HERO_HERE: Schematic showing a CMOS inverter with input and output waveforms, overlaid on a VTC curve graph.]

📘 Microelectronic Circuits Series — Post #35/38 — 16.1-16.4 (Basics)

CMOS logic is the foundational "Lego brick" of every modern CPU, GPU, and microcontroller. Understanding how these switches transition between logic states defines the limits of battery life in your phone and the clock speeds of high-performance servers.

1. Overview & Background — Why this matters

Think of a CMOS inverter like a pair of see-saw riders. The PMOS pull-up transistor sits on the high side (connected to V_DD) and wants to push the output to logic high, while the NMOS pull-down transistor sits on the ground side and wants to pull the output to logic low. Because they are driven by the same input signal, only one rider is "active" at a time: when the input is high, the NMOS is on and the PMOS is off. The output is anchored firmly to ground. When the input is low, the PMOS is on and the NMOS is off; the output is anchored to V_DD.

Figure 1. CMOS inverter circuit (PMOS + NMOS)

Unlike older NMOS-only or bipolar logic, CMOS (Complementary Metal-Oxide-Semiconductor) consumes almost zero static power because there is no direct current path from V_DD to ground in a steady state. This efficiency is precisely why we can pack 50 billion transistors onto a single Apple M3 chip without it melting instantly.

Historically, designers used resistor-pull-up logic, which was hot and slow. The shift to CMOS in the 1980s allowed for the explosion of mobile electronics, as the "complementary" nature—using both p-type and n-type devices—effectively turns each gate into a self-contained, power-efficient switch.

[DIAGRAM_1_HERE: Schematic of a CMOS inverter: PMOS gate/source connected to VDD/Input, NMOS gate/source connected to Ground/Input, both drains tied to Vout.]

2. How it Works (Physical & Circuit Principles)

The Voltage Transfer Characteristic (VTC) is the "signature" of a logic gate. It maps the input voltage V_in to the output voltage V_out. For an ideal inverter, this curve is a sharp "step" function. In reality, as V_in crosses the switching threshold V_M, both the PMOS and NMOS enter the saturation region simultaneously for a brief moment, allowing a spike of short-circuit current.

The switching threshold V_M is defined as the point where V_in = V_out. At this exact voltage, the pull-up and pull-down networks must carry equal current to maintain the equilibrium, assuming balanced design. If the pull-up is stronger (wider PMOS), the threshold shifts toward V_DD; if the pull-down is stronger (wider NMOS), it shifts toward ground.

The noise margins NM_L and NM_H quantify how much "noise" (unwanted voltage spikes) a gate can tolerate before the output logic state becomes ambiguous. We define them based on the unity-gain points of the VTC, where the slope equals -1. If the input is within these margins, the output remains safely in the "0" or "1" logic voltage range.

3. Key Design Equations

The propagation delay t_p, the time it takes for a signal to traverse the gate, is dominated by the time required to charge or discharge the load capacitance C_L through the equivalent resistance R_eq of the transistors.

Figure 2. CMOS inverter VTC with noise margins annotated

where R_eq is the average resistance of the transistor during the switching transition and C_L is the combined gate, interconnect, and diffusion capacitance.

Dynamic power dissipation is the energy lost every time the gate switches state, representing the primary power cost in modern high-speed designs.

where α is the activity factor (probability of switching), and f is the clock frequency.

For complex logic gates, the series or parallel configuration of transistors changes the effective resistance:

where n is the number of NMOS transistors in series, requiring wider devices to maintain the same delay as a single inverter.

4. Worked Numerical Example — Calculate it yourself

Consider an inverter in a 65-nm process with V_DD = 1.0 V. The load capacitance C_L is 10 fF. We assume the average equivalent resistance R_eq for both PMOS and NMOS is 5 kΩ. We operate at a frequency f of 2 GHz with an activity factor α = 0.1.

1. Calculate Propagation Delay: t_p = 0.69 · 5,000 Ω · 10 × 10^-15 F = 34.5 ps. This is the "speed" of the gate.

2. Calculate Dynamic Power: P_dyn = 0.1 · 10 × 10^-15 F · (1.0 V)² · 2 × 10⁹ Hz = 2 μW. This confirms the low power nature of CMOS logic; even at 2 GHz, a single gate consumes mere microwatts.

[DIAGRAM_2_HERE: CMOS NAND (series NMOS) vs. NOR (series PMOS) schematics showing pull-up/pull-down networks.]

5. Design Considerations & Trade-offs

• Stacking: Putting transistors in series (NAND/NOR) increases the total resistance. To keep delay constant, we must increase the width (W) of the transistors to lower their individual resistance.
• Sizing: "Upsizing" transistors reduces R_eq and improves delay but increases C_L for the previous gate, creating a point of diminishing returns in speed optimization.
• V_DD Scaling: Lowering V_DD is the most effective way to reduce dynamic power (due to the square law), but it degrades noise margins and increases delay as the overdrive voltage (V_GS - V_TH) shrinks.
• Leakage: As we shrink to nanometer nodes, "off" current (subthreshold leakage) becomes significant, turning the "static power ≈ 0" assumption into a major design constraint for battery-powered devices.

6. Where it Shows Up in Practice

In the digital I/O block of an ARM Cortex-M4 microcontroller, the output drivers are essentially giant CMOS inverters sized for current drive. In high-performance SoCs, "Standard Cell Libraries" contain thousands of pre-characterized NAND, NOR, and inverter cells—the very gates described here—used by EDA tools to synthesize the entire logic fabric of the chip.

7. Common Pitfalls & Debugging Tips

• ⚠️ The Fan-out Trap: Don't assume an inverter can drive an infinite load. Each additional gate attached to the output adds its input capacitance to C_L, multiplying your delay linearly.
• ⚠️ Floating Inputs: Never leave a CMOS gate input floating. It will drift to an intermediate voltage where both PMOS and NMOS are partially on, potentially leading to massive shoot-through current and chip overheating.

8. Exam & Interview Hot Spots

• 💡 "How does the switching threshold V_M change if you increase the PMOS width (W_p) relative to the NMOS width (W_n)?" (Answer: It shifts toward V_DD).
• 💡 "Why is the dynamic power consumption independent of the transistor size if we ignore self-loading?" (Answer: It depends on the load capacitance, which is often external or determined by interconnects, not the gate size itself).

9. Key Takeaways

• CMOS logic gates utilize complementary pull-up and pull-down networks, ensuring zero static current path.
• The VTC slope is sharpest at V_M; balancing the R_eq of PMOS and NMOS is critical for symmetric performance.
• Propagation delay is a linear function of R_eq · C_L, while dynamic power is proportional to the square of V_DD.
• Logic gates like NAND and NOR require width adjustment to compensate for the resistance added by series-stacked transistors.
• Noise margins define the robustness of the circuit; shrinking V_DD reduces power but tightens these margins.

Educational content only. Always verify with datasheets and SPICE simulation before production design.