[Post #37/38] [Advanced] CMOS Composite CS/CG Topologies

CONTENT_START [HERO_HERE: A high-contrast diagram showing a cascade of CMOS transistors, highlighting the output impedance looking into the drain of a cascode load.]

📘 Microelectronic Circuits Series — Post #37/38 — 17.3-17.4 (Advanced)

Composite CMOS loads represent the pinnacle of gain-stage design, allowing us to reconcile the inherent trade-off between voltage headroom and open-loop gain. Mastering these topologies is essential for any engineer tasked with designing high-performance operational transconductance amplifiers (OTAs) or precision analog-to-digital converters in deep-submicron processes.

1. Overview & Background — Why this matters

Think of a simple Common-Source (CS) amplifier as a basic water faucet. The gate voltage controls the flow (current), and the resistance of the drain load acts like the diameter of the pipe downstream. If the pipe is wide, the water pressure (gain) drops quickly when you open the faucet. A composite load is like adding a pressure-regulating valve downstream that forces the flow to stay constant regardless of the faucet’s position, effectively creating a "stiff" output impedance.

Figure 1. Folded-cascode OTA circuit

In modern CMOS processes, such as 65-nm or 28-nm nodes, the intrinsic gain of a single transistor (g_mr_o) is relatively low because channel length modulation is aggressive. To achieve high voltage gain, we stack transistors into "cascode" structures. These structures are the backbone of high-speed buffers, telescopic cascode amplifiers, and folded-cascode OTAs used in everything from low-noise audio front-ends to high-speed serial links like PCIe PHYs.

[DIAGRAM_1_HERE: Schematic showing an NMOS CS stage with a PMOS cascode current-source load.]

2. How it Works (Physical & Circuit Principles)

The cascode structure works by "shielding" the drain of the input transistor from the output voltage swings. By placing a common-gate transistor in series with the input transistor's drain, we create a high-impedance node that prevents the input device's drain voltage from fluctuating wildly. This isolation keeps the drain-source current of the input transistor steady, satisfying the requirement for high voltage gain, which is defined by the product of transconductance and total output resistance.

where g_m1 is the transconductance of the input driver, R_out,N is the output resistance of the NMOS side, and R_out,P is the resistance of the composite PMOS load.

💡 Intuition: The output resistance of a single MOS transistor is r_o. By adding a cascode device, we multiply the output resistance by the intrinsic gain of the cascode transistor (g_mr_o), turning a mediocre 100 kΩ load into a massive 10 MΩ load. This effectively turns a "leaky" current source into an almost ideal one.

3. Key Design Equations

The small-signal output resistance of a cascode stage is derived from the loop gain of the structure:

Figure 2. Cascode output-impedance analysis (R_out,N and R_out,P labeled)

where g_m,casc is the transconductance of the cascode transistor, and r_o represents the small-signal output resistance of the individual FETs.

where the total gain scales with the square of the intrinsic gain (g_mr_o)² of the transistors.

where V_ov (overdrive voltage) is V_GS - V_TH, showing the direct trade-off between the number of stacked devices and the available output voltage swing.

4. Worked Numerical Example — Calculate it yourself

Consider a 65-nm process where V_DD = 1.2 V. We bias the NMOS input transistor with I_D = 100 μA and a (W/L) = 20/0.18. Assume the intrinsic gain g_mr_o = 20.

Step 1: Calculate r_o. If the early voltage V_A for this process is 10 V/μm, then r_o = V_A·L / I_D = (10 × 0.18) / 100μA = 18 kΩ.

Step 2: Calculate the cascode output resistance. R_out = g_mr_o · r_o = 20 × 18 kΩ = 360 kΩ.

Step 3: Combine with the PMOS load. Assuming the PMOS side is identical, the total resistance is 360 kΩ ∥ 360 kΩ = 180 kΩ.

Step 4: Resulting gain. g_m = 2I_D / V_ov ≈ 200 μA / 0.2 V = 1 mA/V. A_v = -1 mA/V × 180 kΩ = -180 V/V (or 45 dB).

[DIAGRAM_2_HERE: Small-signal model showing the output resistance calculation node.]

5. Design Considerations & Trade-offs

• Headroom: Every added cascode transistor "eats" about V_DS,sat (approx 200 mV) of voltage headroom; in low-voltage designs, this limits the signal range.
• Gain Boosting: By adding an auxiliary amplifier to the gate of the cascode transistor, we can push the output resistance up by an extra factor equal to the auxiliary gain.
• Parasitic Poles: Adding transistors introduces internal nodes (the cascode drain), which create high-frequency poles that can degrade phase margin in negative feedback loops.
• Noise: Every transistor added to the signal path contributes thermal noise (4kTγ/g_m), necessitating a careful balance between bias current and noise requirements.

6. Where it Shows Up in Practice

The folded-cascode architecture is a staple in the input stage of the TI OPA350 high-speed op-amp. It allows for rail-to-rail input common-mode range while maintaining high gain. Similarly, in high-speed ADC design, such as those found in modern cellular base station transceivers, gain-boosted cascode structures are used to achieve the necessary settling accuracy for 12-bit, 100+ MSPS performance.

7. Common Pitfalls & Debugging Tips

• ⚠️ Bias Point Instability: If the cascode bias voltage (V_bias) is not perfectly tied to the supply or a reference, the transistor may drop out of saturation when the output swings, causing severe gain compression.
• ⚠️ Frequency Response: Designers often forget that the cascode node adds a parasitic pole at 1/(R_nodeC_node). Always perform a pole-zero analysis on the intermediate cascode node.

8. Exam & Interview Hot Spots

• 💡 "How does the output impedance of a cascode compare to a simple current source?" (Ans: It is increased by the factor (1 + g_mr_o)).
• 💡 "What is the primary trade-off in gain-boosting?" (Ans: Power consumption and bandwidth—the auxiliary amplifier adds more noise and slows the circuit down).
• 💡 "Why is the folded-cascode preferred over the telescopic cascode for low-voltage supplies?" (Ans: It decouples the input common-mode range from the supply rails).

9. Key Takeaways

• Composite loads turn modest transistors into high-gain building blocks.
• The cascode configuration is the fundamental tool for increasing output resistance and intrinsic gain.
• Gain-boosting can artificially inflate gain but adds power and noise penalties.
• Voltage headroom is the primary constraint when stacking transistors.
• Always simulate the frequency behavior of internal nodes to prevent unexpected peaking in AC response.

Educational content only. Always verify with datasheets and SPICE simulation before production design.