[Post #36/38] [Advanced] IC-Level CMOS Amplifier Bias Design

CONTENT_START [HERO_HERE: Schematic illustration showing a MOSFET Beta-Multiplier cell with an overlaid graph of constant-gm bias characteristics.]

📘 Microelectronic Circuits Series — Post #36/38 — 17.1-17.2 (Advanced)

In analog IC design, bias networks are the "heartbeat" of the system. Without a precise, stable reference current, every amplifier, ADC, and filter on your die will exhibit inconsistent gain, bandwidth, and power consumption across varying temperatures and process corners. Understanding how to derive this reference from the silicon itself is the hallmark of a mature analog design engineer.

1. Overview & Background — Why this matters

Biasing a circuit is like setting the "idle speed" of an engine. If the idle is too low, the engine stalls (the amplifier fails to turn on or enters the subthreshold region unintentionally); if it is too high, you waste fuel and risk overheating (excessive power dissipation). In discrete design, we use high-precision off-chip resistors, but on an integrated circuit, we have limited real estate and poor absolute resistor tolerance, which can vary by ±20% due to manufacturing process spreads.

Figure 1. β-multiplier (constant-g_m) bias circuit with start-up branch

Because we cannot rely on external components for every sub-circuit, we must create a "self-reference"—a circuit that looks at the internal characteristics of the transistors (like threshold voltage V_TH and mobility μ) to generate a constant current. This is the cornerstone of robust System-on-Chip (SoC) design, used in everything from the precision bias of a low-noise amplifier (LNA) in a smartphone's cellular radio to the internal reference generators of high-speed data converters.

[DIAGRAM_1_HERE: A Beta-Multiplier circuit diagram showing two branches with a resistor R_S in the source of one leg and a mirror feedback loop.]

2. How it Works (Physical & Circuit Principles)

The core concept is the β-multiplier, which is like a feedback loop that "self-corrects" its own current based on the physical dimensions of the MOSFETs. We place two branches in a current mirror configuration. By forcing the same current I_REF through both branches but sizing the transistors (W/L ratios) differently, we create a voltage difference across an on-chip resistor R_S. This resistor converts a transconductance-related property into a stable reference current.

The MOSFET drain current in saturation is defined by the square-law model:

where μ_n is electron mobility, C_ox is gate oxide capacitance, W/L is the aspect ratio, and V_GS - V_TH is the overdrive voltage. When we force this current through the source-degenerated resistor R_S, the gate-source voltage V_GS adjusts until the current reaches a stable equilibrium defined solely by the resistor and the transistor geometries.

💡 Intuition: The circuit acts as a self-balancing scale; if the current increases, the voltage drop across R_S increases, which subtracts from the V_GS of the input transistor, thereby pushing the current back down to the set point.

3. Key Design Equations

Assuming a scaling factor K between the two branches (where the second branch is K times wider than the first), the reference current is derived as:

Figure 2. Bandgap voltage-reference block diagram

where K is the ratio of transistor widths (W₂/W₁), and R_S is the degeneration resistor value in Ohms.

The transconductance g_m of the transistors in this loop is set by the geometry and resistor:

where g_m1 is the sensitivity of the drain current to the gate voltage, which remains constant even if the supply voltage V_DD drifts.

4. Worked Numerical Example — Calculate it yourself

Consider a 180-nm CMOS process where μ_nC_ox = 200 μA/V². We choose a resistor R_S = 2 kΩ and a width ratio K = 4 (making the right branch 4× wider than the left). Let the input transistor width ratio be (W/L)₁ = 10/0.5.

Step 1: Calculate the term (1 - 1/√K). For K=4, 1/√4 = 0.5, so (1 - 0.5) = 0.5.

Step 2: Plug into the current equation: I_REF = (2 / (200μ · 20)) · (0.5)² / (2k)².

Step 3: I_REF = (2 / 4000μ) · 0.25 / 4M = 500μA · 0.0625μ = 31.25 μA.

Result: The circuit will stabilize at 31.25 μA, providing a reference current that is independent of V_DD and relatively insensitive to V_TH shifts.

[DIAGRAM_2_HERE: Start-up circuit schematic showing a capacitive or diode-based kick-starter to pull the mirror out of the zero-current state.]

5. Design Considerations & Trade-offs

• Resistor Area Cost: Large values of R_S require significant silicon area. Designers often choose high-sheet-resistance poly-silicon layers to minimize the footprint.
• Accuracy vs. Power: Increasing I_REF improves speed and noise performance but increases static power consumption; R_S must be sized to keep the current within the desired budget.
• Start-up Issues: ⚠️ A Beta-Multiplier has two stable states: the desired operating point and the "off" state (zero current). A start-up circuit is mandatory to pull the gate voltages high upon power-up.
• Supply Sensitivity: While independent of V_DD in theory, channel-length modulation (finite output resistance) causes residual sensitivity. Using cascode current mirrors can mitigate this.

6. Where it Shows Up in Practice

This topology is the bedrock of the Bandgap Voltage Reference (BGR), which provides the 1.2 V reference used in almost all CMOS ADCs. In high-performance SoCs like the Apple M-series processors, constant-g_m biasing is used in the SERDES (Serializer/Deserializer) interfaces to ensure that the input impedance of high-speed ports remains exactly 50 Ω regardless of temperature.

7. Common Pitfalls & Debugging Tips

• ⚠️ Oscillation: If the start-up circuit is too aggressive, it can inject noise into the bias line; ensure the start-up circuit disconnects once the current is established.
• ⚠️ Body Effect: If the sources of the transistors are not tied to the bulk, the threshold voltage V_TH will vary with the source potential, leading to inaccuracies in your I_REF calculation.

8. Exam & Interview Hot Spots

• 💡 "Why do we use a Beta-Multiplier instead of a simple resistor-based bias?" (Answer: To achieve process and temperature independence.)
• 💡 "What is the primary function of the start-up circuit?" (Answer: To prevent the circuit from latching in the zero-current, non-conductive state.)
• 💡 "How does g_m change with temperature in this circuit?" (Answer: It stays largely constant because it is defined by the physical ratio of R_S, which changes less drastically than μ_n.)

9. Key Takeaways

• Beta-multipliers provide self-referenced biasing by leveraging on-chip geometry ratios.
• Constant-g_m bias networks are essential for maintaining stable gain across process corners.
• The I_REF is inversely proportional to R_S², highlighting the critical nature of resistor matching.
• Always implement a start-up circuit; zero-current state is a mathematical possibility in simulations that will crash real hardware.
• Use cascoding to improve power supply rejection (PSRR) if your application involves high-precision analog signals.

Educational content only. Always verify with datasheets and SPICE simulation before production design.